1. Field of the Invention
The present invention relates to an internal clock signal generating circuit. More specifically, the present invention relates to an internal clock signal generating circuit for generating, in synchronization with an externally applied clock signal, signals which are multiplication of the externally applied clock signal.
2. Description of the Background Art
As speed of operation of microprocessors has been ever increasing, increase in speed of internal clock signals for operating overall system including a semiconductor memory device has come to be a critical problem in view of the system performance. This is because the internal clock signal restricts operational frequency of the overall system in relation to the access time.
To meet the demand of higher internal clock signals, a delay lock loop (hereinafter referred to as DLL circuit) has been proposed as an internal clock signal generating circuit which receives an externally applied clock signal (external clock signal) and generates an internal clock signal which is in synchronization with the external clock signal.
In the following, a structure of the conventional DLL circuit will be described with reference to FIG. 17.
The conventional DLL circuit 900 shown in FIG. 17 includes a delay line 2, a shift register 4, a phase comparator 16 and a delay circuit 8. DLL circuit 900 is a digital type DLL circuit which suppresses power supply noise more effectively than an analog type DLL circuit.
Delay line 2 delays an input external clock signal EXTCLK and outputs an internal clock signal INTCLK 1. Delay circuit 8 delays internal clock signal INTCLK 1 by td2 and outputs the resulting signal (clock signal INTCLK 2).
Phase comparator 16 compares phases of external clock signal EXTCLK and of clock signal INTCLK 2 output from delay circuit 8. As a result of phase comparison, phase comparator 16 outputs an UP signal or a DOWN signal. Shift register 4 receives at its input the UP signal or the DOWN signal output from phase comparator 16, and changes delay time of delay line 2.
Structure of delay line 2 and a relation with shift register 4 will be described with reference to FIG. 18.
Delay line 2 shown in FIG. 18 includes a plurality of delay units U0, U1, . . . , Un, elements D0, D1, . . . , Dn and a plurality of NMOS transistors N1.0, N1.1, . . . , N1.n. In the following, delay units U0, U1, . . . , Un will be generally referred to as delay unit U, and elements D0, D1, . . . , Dn as element D.
Each delay unit U includes inverter circuits 40 and 41. Elements D0, D1, . . . , Dn are connected to output nodes of corresponding delay units U0, U1, . . . , Un, respectively. NMOS transistors N1.0, N1.1, . . . , N1.n are connected between a signal line a10 and corresponding elements D, respectively.
Delay unit U0 receives a clock signal (in FIG. 18, IN). Over signal line a10, a signal (in FIG. 18, OUT) is output.
Shift register 4 includes a plurality of registers L0, L1, . . . , Ln. In the following, registers L0, L1, . . . , Ln will be generally referred to as register L.
Registers L0, L1, . . . , Ln are provided corresponding to NMOS transistors N1.0, N1.1, . . . , N1.n, respectively. NMOS transistors N1.0, N1.1, . . . , N1.n receive at respective gate electrodes, corresponding control signals d(0), d(1), . . . , d(n) from corresponding registers L.
Any one of the control signals d(0), d(1), . . . , d(n) output from shift register 4 is in an active state. In response to control signals d(0), d(1), . . . , d(n), the number of delay units U through which input signal IN is passed is determined.
The structure of shift register 4 will be described with reference to FIG. 19.
As shown in FIG. 19, shift register 4 includes a plurality of registers L0, L1, L3, . . . , and a logic gate 47.
Logic gate 47 receives at its input the DOWN signal and the UP signal output from phase comparator 16, and outputs a signal T0. Registers L (except L0) each include an NAND circuit 43, inverter circuits 44, 45 and 46, and NMOS transistors N2, N3 and N4.
A first input node of each NAND circuit 43 receives a reset signal ZRST. Each NMOS transistor N3 receives at its gate electrode the DOWN signal output from phase comparator 16. Each NMOS transistor N4 receives at its gate electrode the UP signal output from phase comparator 16. Each NMOS transistor N2 receives at its gate electrode the signal T0 output from logic gate 47.
Circuit structure of the register will be described, taking register L2 as a representative example. NAND circuit 43 has a second input node connected to a node O2 (connection node between register L2 and register L1 of the preceding stage).
Inverter circuit 44 is connected between a node O2 and an output node of NAND circuit 43. NMOS transistor N2 is connected between inverter circuit 45 and NAND circuit 43. Inverter circuit 46 is connected between an output node and an input node of inverter circuit 45.
NMOS transistor N3 is connected between a node O3 (connection node between register L2 and register L3 of the succeeding stage) and inverter circuit 45. NMOS transistor N4 is connected between inverter circuit 45 and a node O1 (connection node between registers L0 and L1).
In shift register L0, an output node of NAND circuit 43 is connected to a node O0. Inverter circuit 44 is connected between node O0 and the second input node of NAND circuit 43. NMOS transistor N2 is connected between inverter circuits 45 and 44. It does not include NMOS transistor N4 for receiving the UP signal.
Between a node O0 and a ground potential GND, an NMOS transistor N3 receiving the DOWN signal is arranged.
Control signals d(0), d(1), . . . are output from corresponding output nodes (input nodes of inverter circuit 46) of respective inverter circuits 45 of registers L.
In the following, output signals from NAND circuits 43 in respective registers L1, L2, . . . will be represented as s(1), s(2), . . . , and the output signal from inverter circuit 44 in register L0 will be represented as s(0).
The operation of shift register 4 will be described with reference to timing charts of FIGS. 20A to 20L.
Referring to FIGS. 20A to 20L, at time t0, reset signal ZRST is set to an L (low) level. Consequently, shift register 4 is set to an initial state. Signal d(0) is set to 1. A signal d(k) (where 1&lt;k.ltoreq.n) is set to 0.
Thereafter, reset signal ZRST is set to an H (high) level.
Thereafter, at time t1, when DOWN signal rises to the H level, a signal T0 falls to the L level.
In response to control signal d(m), a signal s(m+1) (where 1.ltoreq.m.ltoreq.n-1) makes a transition. More specifically, upon reception of control signal d(0), signal s(1) goes from 1 to 0, as shown in FIGS. 20F and 20G.
Thereafter, at time t2, when DOWN signal falls to the L level, signal T0 rises to the H level.
In response to signal s(m), control signal d(m) (where 0.ltoreq.m.ltoreq.n) changes. More specifically, in response to signal s(0), control signal d(0) changes from 1 to 0 as shown in FIGS. 20E and 20F.
In the similar manner thereafter, when DOWN signal rises to the H signal, signal s(m+1) changes in response to control signal d(m) (where 0.ltoreq.m.ltoreq.n-1) in synchronization with the rising edge of DOWN signal.
When DOWN signal falls to the L level, control signal d(i) changes in response to signal s(i) (where 0.ltoreq.i.ltoreq.n) in synchronization with the falling edge of DOWN signal.
More specifically, in synchronization with the rising edge of DOWN signal, state of the control signal is transferred in one direction (from d(m) to d(m+1)).
When UP signal rises to the H level, signal s(x-1) changes in response to control signal d(x) (where 1.ltoreq.x.ltoreq.n) in synchronization with the rising edge of UP signal.
When UP signal falls to the L level, control signal d(i) changes in response to signal s(i) (where 0.ltoreq.i.ltoreq.n) in synchronization with the falling edge of UP signal.
More specifically, state of the control signal is transferred in the other direction (from d(x) to d(x-1)) in synchronization with the rising edge of UP signal.
The operation of the conventional DLL circuit 900 will be briefly described with reference to timing charts of FIGS. 21A to 21C.
Delay time of delay line 2 is represented as td0. Delay time of delay circuit 8 is represented as td2.
Referring to FIGS. 21A to 21C, for a kth external clock signal, a kth internal clock signal INTCLK 1 is generated. For the kth internal clock signal INTCLK 1, a kth clock signal INTCLK 2 is generated.
More specifically, when a first external clock signal EXTCLK is input, a first internal clock signal INTCLK 1 is output after the lapse of td0. Further, a first clock signal INTCLK 2 is output after the lapse of td2.
When a second external clock signal EXTCLK is input, a second internal clock signal INTCLK 1 is output after the lapse of td0, and a second clock signal INTCLK 2 is output after the lapse of td2.
Here, phase comparator 16 detects phase difference between clock signal INTCLK 2 and external clock signal EXTCLK. As a result, delay time of delay line 2 is adjusted (delay time td1).
Interconnection for interface between semiconductor memory devices comes to be longer and the number of branches connecting buses has been increasing. Therefore, increase in operational frequency of the semiconductor memory device comes to be increasingly difficult.
In view of the foregoing, in order to improve system performance, a desired clock is internally generated to increase operational frequency.
A DLL circuit for generating multiplied clock signals will be described with reference to FIG. 22. DLL circuit 910 shown in FIG. 22 includes a delay line 22, a selector 17, a phase comparator 16 and an OR circuit 19.
Delay line 12 outputs internal clock signals INTCLK and INTCLK 3. When delay time for internal clock signal INTCLK is given as td, delay time for internal clock signal INTCLK 3 is td/2.
OR circuit 19 receives internal clock signals INTCLK and INTCLK 3, and outputs internal clock signal INTCLK 2.
Basic structure of delay line 12 and the relation with selector 17 will be described with reference to FIG. 23.
Selector 17 shown in FIG. 23 may have the same structure as shift register 4 described above. Selector 17 outputs control signals d(0), d(1), d(2), . . . , d(n) in response to DOWN signal or UP signal output from phase comparator 16. Any of control signals d(0), d(1), d(2), . . . , d(n) is in an active state. The active state moves in accordance with the DOWN signal or the UP signal.
Delay line 12 includes delay portions 14 and 15. Basic structure of delay portions 14 and 15 is the same as delay line 2 shown in FIG. 18.
Delay portion 14 receives an external input signal (in FIG. 23, DIN), and outputs internal clock signal INTCLK 3 through signal line a10.
Delay portion 15 has its input node connected to signal line a10 of delay portion 14. In delay portion 15, internal clock signal INTCLK is output from a signal line a11.
More specifically, in DLL circuit 910, the delay line is divided into two (delay portions 14, 15), and positions where signals are taken out are made the same in delay portions 14 and 15, whereby signals having phases shifted by 180.degree. from each other are generated.
The operation of the conventional DLL circuit 910 will be described with reference to the timing charts of FIGS. 24A to 24D.
In the figures, external clock signal EXTCLK and internal clock signal INTCLK are shown in phase with each other.
Referring to FIGS. 24A to 24D, when external clock signal EXTCLK is input, after a period td/2, internal clock signal INTCLK 3 is generated. After a period td, internal clock signal INTCLK is generated.
As a result, by obtaining sum of internal clock signals INTCLK 3 and INTCLK through OR circuit 19, an internal clock signal (INTCLK 2) multiplied by 2 is obtained.
U.S. Pat. No. 5,548,235 entitled "Phase-Locked Loop and Resulting Frequency Multiplier" discloses a circuit for generating clock signals multiplied by two by dividing a delay line.
However, when internal clock signals multiplied by two are generated by dividing a delay line, accuracy in multiplication may possibly be degraded, since signals are passed through different delay lines.
An example in which delay accuracy in delay portions 14 and 15 involved with delay line 12 differ from each other because of process variation or the like in conventional DLL circuit 910 shown in FIG. 23 will be briefly described with reference to the timing charts of FIGS. 25A to 25D.
In this case, as shown in FIGS. 25A to 25D, internal clock signal INTCLK is generated delayed by td from external clock signal EXTCLK. Meanwhile, internal clock signal INTCLK 3 is generated delayed by td1 from external clock signal EXTCLK. However, because of different delay accuracy, relation between the time periods would be td1.noteq.td/2. As a result, desired clock signals multiplied by two cannot be obtained.